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| hyb18h1g321a2f?08 hyb18h1g321a2f?10 hyb18h1g321a2f?14 gddr3 graphics ram 1-gbit gddr3 graphics ram eu rohs compliant advance internet data sheet rev. 0.61 october 2008
advance internet data sheet hyb18h1g321a2f 1-gbit gddr3 graphics ram qag_techdoc_a4, 4.22, 2008-07-22 2 10102008-h7r1-i6ah we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com hyb18h1g321a2f?08, hyb18h1g321a2f?10, hyb18h1g321a2f?14 revision history: 2008-10, rev. 0.61 page subjects (major chang es since last revision) all adapted internet version hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 3 10102008-h7r1-i6ah 1overview this chapter lists all main features of the product family hyb18h1g321a2f and the ordering information. 1.1 features ? 1.8 v and 1.5 v v ddq io voltage hyb18h1g321a2f?08 ? 1.8 v and 1.5 v v dd core voltage hyb18h1g321a2f?08 ? monolithic 1gbit gddr3 with an internally programmable organization of either two separate 512mbit memories (2048 k x 32 i/o x 8 banks) with separate chip select, or one 1gb memory (4096 k x 32 i/o x 8 banks) ? two cs: 4096 rows and 512 columns (128 burst start locations) per bank ? one cs: 8192 rows and 512 columns (128 burst start locations) per bank ? differential clock inputs (clk and clk ) ? cas latencies of 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 ? write latencies of 3, 4, 5, 6, 7 ? burst sequence with length of 4, 8 ? 4n pre fetch ? short ras to cas timing for writes ? t ras lockout support ? t wr programmable for writes with auto-precharge ? data mask for write commands ? single ended read strobe (rdqs) per byte. rdqs edge- aligned with read data ? single ended write strobe (wdqs) per byte. wdqs center-aligned with write data ? dll aligns rdqs and dq transitions with clock ? programmable io interface including on chip termination (odt) ? autoprecharge option with co ncurrent auto precharge support ? 8k refresh (32ms) ? autorefresh and self refresh ? pg-tfbga-136 package ? calibrated output drive. active termination support ? rohs compliant product 1) 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 4 10102008-h7r1-i6ah table 1 ordering information part number 1) 1) hyb: designator for memory components 18h: v dd / v ddq = 1.8v 1g: 1 gbit 32: x32 organization a2: product revision f: lead and halogen-free organization clock (mhz) package hyb18h1g321a2f?08 32 1200 @ cl15, 1.8 v pg-tfbga-136 900 @ cl11, 1.5 v hyb18h1g321a2f?10 x32 1000 @ cl12, 1.8 v 800 @ cl10, 1.5 v hyb18h1g321a2f?14 x32 700 @ cl10, 1.8 v 700 @ cl10, 1.5 v hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 5 10102008-h7r1-i6ah 1.2 description the qimonda 1-gbit gddr3 graphics ram is a high speed memory device, designed for high bandwidth intensive applications like pc graphics systems. the chip is programmable into two different configurations. in the default mode the architecture is organized as two 512 mbit me mories of 8 banks, each (two cs mode). in an alternate configuration, it behaves as a conventional, 8-bank 1 gbit dram (one cs mode). hyb18h1g321a2f uses a double data rate interface and a 4 n -pre fetch architecture. the gddr3 interface transfers two 32 bit wide data words per clock cycle to/fro m the i/o pins. corresponding to the 4 n -pre fetch a single write or read access consists of a 128 bit wide, one-clock-cycle data transfer at the internal me mory core and four corresponding 32 bit wide, one-half-clock - cycle data transfers at the i/o pins. single-ended unidirectional read and write data strobes are transmitted simultaneously with read and write data respectively in order to capture data properly at the receivers of both the graphics sdram and the controller . data strobes are organized per byte of the 32 bit wide interface. for read commands th e rdqs are edge-aligned with data, and the wdqs are center- aligned with data for write commands. the hyb18h1g321a2f operates from a differential clock (clk and clk ). commands (addresses and control signals) are registered at every positive edge of clk. input data is registered on both edges of wdqs, and output data is referenced to both edges of rdqs. in this document references to ?the positive edge of clk? impl y the crossing of the positive edge of clk and the negative edge of clk . similarly, the ?negative edge of clk? refers to the crossing of the negative e dge of clk and the positive edge of clk . references to rdqs are to be interpreted as any or all rdqs< 3:0>. wdqs, dm and dq should be interpreted in a similar fashion. read and write accesses to the hyb18h1g321a2f are burst ori ented. the burst length is fixed to 4 and 8 and the two least significant bits of the burst address are ?don?t care? and inte rnally set to low. accesses begin with the registration of an activate command, which is then followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and the row to be accessed. the address bits registered coincident with the read or write command are used to sele ct the bank and the column location for the burst access. in two cs mode, each of the 2 x 8 banks consists of 4096 row locations and 512 column locations. in one cs mode, the number of row locations doubles to 8192 rows while the number of column location remains unchanged at 512 columns. an auto precharge function can be combined with read and write to provide a self-timed row prec harge that is initiated at th e end of the burst access. the pipe lined, multibank architecture of the hyb18h1g321a2f allows for concurrent operation, t hereby providing high effective bandwidth by hiding row precharge and activation time. the ?on die termination? interface (odt) is optimized for high fr equency digital data transfers and is internally controlled. t he termination resistor value can be set using an external zq re sistor or disabled through the extended mode register. the output driver impedance can be set using the extended mode register. it can either be set to zq / 6 (auto calibration) or to 35, 40 or 45 ohms. auto refresh and power down with self refresh operations are supported. an industrial standard pg-tfbga-136 package is used which enables ultra high speed data transfer rates and a simple upgrade path from former ddr graphics sdram products. hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 6 10102008-h7r1-i6ah 2 configuration figure 1 ballout 1-gbit gddr3 graphics ram in 1-cs mode in non merged mode(top view; mf = low) 0 3 3 * & . ( 9 ' ' 9 6 6 % $ & . $ $ ' 0 ' 4 ' 4 9 6 6 4 ' 0 ' 4 ' 4 ' 4 ' 4 9 5 ( ) 9 6 6 4 9 ' ' 4 9 6 6 4 9 6 6 $ $ $ $ $ $ 9 6 6 5 ' 4 6 ' 4 ' 4 9 6 6 % $ ' 4 ' 4 0 ) 9 ' ' ' 0 ' 4 9 6 6 4 9 ' ' 4 9 6 6 9 ' ' 9 ' ' 4 9 ' ' 4 ' 4 ' 4 ' 4 ' 4 = 4 ' 4 9 ' ' 4 ' 4 9 ' ' 4 9 6 6 4 : ' 4 6 9 6 6 4 9 ' ' 4 9 ' ' 4 9 ' ' 9 6 6 9 6 6 4 5 $ 5 9 ' ' 4 9 ' ' $ $ 9 ' ' ' 4 $ 9 ' ' 4 ' 4 ' 0 9 ' ' 4 9 6 6 4 : ' 4 6 5 ' 4 6 9 6 6 4 9 ' ' 4 ' 4 ' 4 9 ' ' 4 9 6 6 4 ' 4 ' 4 9 6 6 4 9 ' ' 4 9 ' ' 9 6 6 6 ( 1 9 6 6 4 9 ' ' 4 ' 4 9 ' ' 4 9 6 6 4 5 ' 4 6 : ' 4 6 9 6 6 4 9 ' ' 4 9 ' ' 4 & $ 6 5 $ 6 ' 4 9 ' ' : ( 9 6 6 4 % $ 9 5 ( ) 9 ' ' 4 & . 9 6 6 $ $ $ 3 9 ' ' 9 6 6 4 9 6 6 ' 4 ' 4 ' 4 9 ' ' 4 9 6 6 4 5 ' 4 6 : ' 4 6 9 6 6 4 ' 4 ' 4 9 ' ' 4 9 6 6 4 ' 4 ' 4 9 6 6 4 5 ( 6 ( 7 9 6 6 9 ' ' 9 ' ' 4 $ % & ' ) * + - ( / 0 . 1 3 7 9 5 & 6 hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 7 10102008-h7r1-i6ah figure 2 ballout 1-gbit gddr3 graphics ram in 2-cs mode in non merged mode(top view; mf = low) 0 3 3 * & . ( 9 ' ' 9 6 6 % $ & . $ $ ' 0 ' 4 ' 4 9 6 6 4 ' 0 ' 4 ' 4 ' 4 ' 4 9 5 ( ) 9 6 6 4 9 ' ' 4 9 6 6 4 9 6 6 $ 5 $ 5 $ $ $ $ 9 6 6 5 ' 4 6 ' 4 ' 4 9 6 6 % $ ' 4 ' 4 0 ) 9 ' ' ' 0 ' 4 9 6 6 4 9 ' ' 4 9 6 6 9 ' ' 9 ' ' 4 9 ' ' 4 ' 4 ' 4 ' 4 ' 4 = 4 ' 4 9 ' ' 4 ' 4 9 ' ' 4 9 6 6 4 : ' 4 6 9 6 6 4 9 ' ' 4 9 ' ' 4 9 ' ' 9 6 6 9 6 6 4 & 6 9 ' ' 4 9 ' ' $ $ 9 ' ' ' 4 $ 9 ' ' 4 ' 4 ' 0 9 ' ' 4 9 6 6 4 : ' 4 6 5 ' 4 6 9 6 6 4 9 ' ' 4 ' 4 ' 4 9 ' ' 4 9 6 6 4 ' 4 ' 4 9 6 6 4 9 ' ' 4 9 ' ' 9 6 6 6 ( 1 9 6 6 4 9 ' ' 4 ' 4 9 ' ' 4 9 6 6 4 5 ' 4 6 : ' 4 6 9 6 6 4 9 ' ' 4 9 ' ' 4 & $ 6 5 $ 6 ' 4 9 ' ' : ( 9 6 6 4 % $ 9 5 ( ) 9 ' ' 4 & . 9 6 6 $ $ $ 3 9 ' ' 9 6 6 4 9 6 6 ' 4 ' 4 ' 4 9 ' ' 4 9 6 6 4 5 ' 4 6 : ' 4 6 9 6 6 4 ' 4 ' 4 9 ' ' 4 9 6 6 4 ' 4 ' 4 9 6 6 4 5 ( 6 ( 7 9 6 6 9 ' ' 9 ' ' 4 $ % & ' ) * + - ( / 0 . 1 3 7 9 5 & 6 hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 8 10102008-h7r1-i6ah figure 3 ballout 1gbit gddr3 graphics ram in merged mode 0 3 3 * & . ( 9 ' ' 9 6 6 % $ & . $ $ ' 0 ' 4 ' 4 9 6 6 4 ' 0 ' 4 ' 4 ' 4 ' 4 9 5 ( ) 9 6 6 4 9 ' ' 4 9 6 6 4 9 6 6 $ 5 ) 8 $ $ $ $ 9 6 6 5 ' 4 6 ' 4 ' 4 9 6 6 % $ ' 4 ' 4 0 ) 9 ' ' ' 0 ' 4 9 6 6 4 9 ' ' 4 9 6 6 9 ' ' 9 ' ' 4 9 ' ' 4 ' 4 ' 4 ' 4 ' 4 = 4 ' 4 9 ' ' 4 ' 4 9 ' ' 4 9 6 6 4 : ' 4 6 9 6 6 4 9 ' ' 4 9 ' ' 4 9 ' ' 9 6 6 9 6 6 4 $ & 6 9 ' ' 4 9 ' ' $ $ 9 ' ' ' 4 $ 9 ' ' 4 ' 4 ' 0 9 ' ' 4 9 6 6 4 : ' 4 6 5 ' 4 6 9 6 6 4 9 ' ' 4 ' 4 ' 4 9 ' ' 4 9 6 6 4 ' 4 ' 4 9 6 6 4 9 ' ' 4 9 ' ' 9 6 6 6 ( 1 9 6 6 4 9 ' ' 4 ' 4 9 ' ' 4 9 6 6 4 5 ' 4 6 : ' 4 6 9 6 6 4 9 ' ' 4 9 ' ' 4 & $ 6 5 $ 6 ' 4 9 ' ' : ( 9 6 6 4 % $ 9 5 ( ) 9 ' ' 4 & . 9 6 6 $ $ $ 3 9 ' ' 9 6 6 4 9 6 6 ' 4 ' 4 ' 4 9 ' ' 4 9 6 6 4 5 ' 4 6 : ' 4 6 9 6 6 4 ' 4 ' 4 9 ' ' 4 9 6 6 4 ' 4 ' 4 9 6 6 4 5 ( 6 ( 7 9 6 6 9 ' ' 9 ' ' 4 $ % & ' ) * + - ( / 0 . 1 3 7 9 5 & 6 hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 9 10102008-h7r1-i6ah 2.1 ball definition and description table 2 ball description ball type detailed function clk, clk input clock: clk and clk are differential clock inputs. address and command inputs are latched on the positive edge of clk. graphics sdram out puts (rdqs, dqs) are referenced to clk. clk and clk are not internally terminated. cke input clock enable: cke high activates and cke low deactivates t he internal clock and input buffers. taking cke low provides power down. if all banks are precha rged, this mode is called precharge power down and self refresh mode is entered if a auto refres h command is issued. if at least one bank is open, active power down mode is entered and no self refr esh is allowed. all input receivers except clk, clk and cke are disabled during power down. in self refresh mode the clock receivers are disabled too. self refresh exit is performed by setting cke asynchronously high. exit of power down without self refresh is accomplished by setting cke high with a positive edge of clk. the value of cke is latched asynchronously by reset during power on to determine the value of the termination resistor of the address and command inputs. cke is not allowed to go low durin g a rd, a wr or a snoop burst. cs0 input chip select: cs0 enables the command decoder when low and disables it when high. when the command decoder is disabled, new commands with the exce ption of dterdis are ignored, but internal operations continue. in 2-cs mode, cs0 is exclusively used for mrs, emrs and srefen. cs1 input chip select: cs1 is only evaluated in 2-cs mode, and it is used as the chip-select signal for the second memory block. ras , cas , we input command inputs: sampled at the positive edge of clk, cas , ras , and we define (together with corresponding cs ) the command to be executed. dq<0:31> i/o data inputs/outputs: the dq signals form the 32 bit data bus. duri ng reads the balls are outputs and during writes they are inputs. data is tran sferred at both edges of rdqs. dm<0:3> input input data masks: the dm signals are input mask signals for write data. data is masked when dm is sampled high with the write data. dm is sampled on both edges of wdqs. dm0 is for dq<0:7>, dm1 is for dq<8:15>, dm2 is for dq<16:23> and dm3 is fo r dq<24:31>. although dm balls are input-only, their loading is designed to match the dq and wdqs balls. rdqs<0:3> output read data strobes: rdqsx are unidirectional strobe signals. during reads the rdqsx are tran smitted by the graphics sdram and edge-aligned with data. rdqs have pream ble and postamble requirements. rdqs0 is for dq<0:7>, rdqs1 for dq<8:15>, rdqs2 for dq<16:23> and rdqs3 for dq<24:31>. wdqs<0:3> input write data strobes: wdqsx are unidirectional strobe signals. du ring writes the wdqsx are generated by the controller and center aligned with data. wdqs have preamble and postamble requirements. wdqs0 is for dq<0:7>, wdqs1 for dq<8:1 5>, wdqs2 for dq<16:23> and wdqs3 for dq<24:31>. hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 10 10102008-h7r1-i6ah ba<0:2> input bank address inputs: ba select to which internal bank an activate, read, write or precharge command is being applied. ba are also used to distinguish between the mode register set and extended mode register set commands. a<0:11> input address inputs: during activate, a0-a11 defines the row addre ss. for read/write, a2-a7 and a9 defines the column address, and a8 defines the auto precharge bit. if a8 is high, the accessed bank is precharged after execution of the column access. if a8 is low, auto precharge is disabled and the bank remains active. sampled with pre charge, a8 determines whether one bank is precharged (selected by ba<0:2>, a8 low) or all 8 banks are precharged (a8 high). during (extended) mode register set the address inpu ts define the register settings. a<0:11> are sampled with the positive edge of clk. a<12> input address inputs: a12 define the msb of the row address during an activate in 1-cs mode. zq - odt impedance reference: the zq ball is used to control the odt impedance. reset input reset pin: the res pin is a v ddq cmos input. res is not internally te rminated. when res is at low state the chip goes into full reset. the chip stays in full reset until res goes to high state. the low to high transition of the res signal is used to latch the cke value to set the value of the termination resistors of the address and command inputs. after exiting th e full reset a complete initialization is required since the full reset sets the internal settings to default, including mode register bits. mf input mirror function pin: the mf pin is a v ddq cmos input. this pin must be hardwired on board either to a power or to a ground plane. with mf set to high, the command and address pins are reassigned in order to allow for an easier routing on board for a back to back memory arrangement. sen input enables boundary scan functionality: if boundary scan is not used pin should be constantly connected to gnd. v ref supply voltage reference: v ref is the reference voltage input. v dd , v ss supply power supply: power and ground for the internal logic. v ddq , v ssq supply i/o power supply: isolated power and ground for the output buffe rs to provide improved noise immunity. nc, rfu - please do not connect. reserved for future use balls. rar reserved for alternate rank ball type detailed function hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 11 10102008-h7r1-i6ah 2.2 mirror function the gddr3 graphics ram provides a ball mirro ring feature that is enabl ed by applying a logic high on ball mf. this function allows for efficient routing in a clam shell configuration. depending of the logic state applied on mf, the command and address signals will be assigned to different balls. the default ball configuration (see figure 1 , figure 2 and figure 3 ) corresponds to mf = low. the cs1 and a12 balls are not mirrored. the dc level (high or low) must be applied on the mf pi n at power up and is not allowed to change after that. table 3 shows the ball assignment as a function of the logic state applied on mf. table 3 ball assignment with mirror mf logic state signal low high h3 h10 ras f4 f9 cas h9 h4 we f9 f4 cs 0 h4 h9 cke k4 k9 a0 h2 h11 a1 k3 k10 a2 m4 m9 a3 k9 k4 a4 h11 h2 a5 k10 k3 a6 l9 l4 a7 k11 k2 a8 m9 m4 a9 k2 k11 a10 l4 l9 a11 g4 g9 ba0 g9 g4 ba1 h10 h3 ba2 hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 12 10102008-h7r1-i6ah 2.3 commands 2.3.1 command table in the following table cken refers to the positive edge of clk corresponding to the clock cycle when the command is given to the graphics sdram. cken-1 refers to the previous positi ve edge of clk. for all command and address inputs cken is implied. all input states or sequences not shown are illegal or reserved. table 4 command overview for 1-cs mode operation code cke n-1 cke n bcs0 bras bcas bwe ba0 ba1 ba2 a8 a2-7 a9-11/12 note device delselect desel h h h l x h x x h x l h xxxx x 1) 1) x represents ?don?t care?. data terminator disable dterdis h h h h l h x x x x x 1)2) 2) this command is invoked when a read is issued on another dram rank placed on the same command bus. cannot be in power-down or self-refresh state. the read command will cause the data termination to be disabled. no operation nop h h l h h h x x x x x mode register set mrs h h l l l l 0 0 0 opcode extended mode register set emrs h h l l l l 1 0 opcode extended mode register set 2 emrs2 h h l l l l 0 1 0 opcode extended mode register set 3 emrs3 h h l l l l 1 1 0 opcode bank activate act h h l l h h ba ba ba row adress 1)3) 3) ba0 - ba2 provide bank address, a0 - a11, a12 provide the row address. read rd h h l h l h ba ba ba l col. read w/ autoprecharge rd/a h h l h l h ba ba ba h col. write wr h h l h ll bababal col. 1)4) 4) ba0 - ba2 provide bank address, a2 - a7, a9 provide the column address, a8/ap controls auto precharge. write w/ autoprecharge wr/a h h l h l l ba ba ba h col. precharge pre h h l l h l ba ba ba l x 1)4) precharge all preall h h l l h l x x x h x auto refresh aref h h l l l h x x x x x 1)5) power down mode entry pwdnen h l h l x h x h x h xxxx x 1)6) power down mode exit pwdnex l h x x x x x x x x x 1)7) self refresh entry srefen h l l l l h x x x x x 1)8) self refresh exit srefex l h x x x x x x x x x 1)9) hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 13 10102008-h7r1-i6ah table 5 command overview for 2-cs mode 5) auto refresh and self refresh entry differ only by the state of cke. 6) pwdnen is selected by issuing a desel or nop at the firs t positive clk edge following the high to low transition of cke. 7) first possible valid command after t xpn . during t xpn only nop or desel commands are allowed. 8) self refresh is selected by issuing aref at the first positive clk edge following the high to low transition of cke. 9) first possible valid command after t xsc . during t xsc only nop or desel commands are allowed. operation code ranks cke n-1 cke bcs0 bcs1 bras bcas bwe ba0 ba1 ba2 a8 a2-7 a9-11 note device deselect desel h h h h l x h x x h x l h xxxx x 1) data terminator disable dterdis h h h h h l h x x x x x 1)2) no operation nop h h l x x l hhhxxxx x mode register set mrs h h l x l l l 0 0 0 opcode extended mode register set emrs h h l x l l l 1 0 opcode extended mode register set 2 emrs2 h h l x l l l 0 1 0 opcode extended mode register set 3 emrs3 h h l x l l l 1 1 0 opcode bank activate act memblock 1 h h l h l h h ba ba ba row address 1)3) memblock 2 h h h l l h h ba ba ba row address read rd memblock 1 h h l h h l h ba ba ba l col. 1)4) memblock 2 h h h l h l h ba ba ba l col. read w/ autoprecharge rd/a memblock 1 h h l h h l h ba ba ba h col. 1)4) memblock 2 h h h l h l h ba ba ba h col. write wr memblock 1 h h l h h l l ba ba ba l col. 1)4) memblock 2 h h h l h l l ba ba ba l col. write w/ autoprecharge wr/a memblock 1 h h l h h l l ba ba ba h col. 1)4) memblock 2 h h h l h l l ba ba ba h col. precharge pre memblock 1 h h l h l h l ba ba ba l x 1) memblock 2 h h h l l h l ba ba ba l x both h h l l l h l bababal x precharge all preall memblock 1 h h l h l h l x x x h x 1) memblock 2 h h h l l h l x x x h x both h hlllhlxxxh x auto refresh aref memblock 1 h h l h l l h x x x x x 1)5) memblock 2 h h h l l l h x x x x x both h hllllhxxxx x power down mode entry pwdnen h l h x l h l x x h x h x h xxxx x 1)6) hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 14 10102008-h7r1-i6ah power down mode exit pwdnex l h x x x x x x x x x x 1)7) self refresh entry srefen h l l l l l h x x x x x 1)8) self refresh exit srefex l h x x x x x x x x x x 1)9) 1) x represents ?don?t care?. 2) this command is invoked when a read is issued on another dram rank placed on the same command bus. cannot be in power-down or self-refresh state. the read command will cause the data termination to be disabled. refer to figure 15 for timing. 3) ba0 - ba2 provide bank address, a0 - a11, a12 provide the row address. 4) ba0 - ba2 provide bank address, a2 - a7, a9 provide the column address, a8/ap controls auto precharge. 5) auto refresh and self refresh entry differ only by the state of cke. 6) pwdnen is selected by issuing a desel or nop at the firs t positive clk edge following the high to low transition of cke. 7) first possible valid command after t xpn . during t xpn only nop or desel commands are allowed. 8) self refresh is selected by issuing aref at the first positive clk edge following the high to low transition of cke. 9) first possible valid command after t xsc . during t xsc only nop or desel commands are allowed. operation code ranks cke n-1 cke bcs0 bcs1 bras bcas bwe ba0 ba1 ba2 a8 a2-7 a9-11 note hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 15 10102008-h7r1-i6ah 2.4 truth tables 2.4.1 function truth table for more than one activated bank if there is more than one bank activated in the graphics sdram, some commands can be performed in parallel due to the chip?s multibank architecture. the following table defines for which commands such a scheme is possible. all other transitions are illegal. notes 1-11 define the start and end of the action s belonging to a submitted command. this table is based on the assumption that there are no other actions ongoing on bank n or bank m. if there are any actions ongoing on a third bank t rrd , t rtw and t wtr have to be taken always into account. table 6 function truth table i current state ongoing action on bank n possible action in parallel on bank m active activate 1) 1) action activate starts with issuing the command and ends after t rcd . act, pre, write, write/a, read, read/a 2) 2) during action activate an act command on another bank is allowed considering t rrd or t rrd_rr , a pre command on another bank is allowed any time. wr, wr/a, rd and rd/a are always allowed. write 3) 3) action write starts with issuing the command and ends twr afte r the first pos. edge of clk following the last falling wdqs ed ge. act, pre, write, write/a, read, read/a 4) 4) during action write an act or a pre command on another bank is allowed any time. a new wr or wr/a command on another bank must be separated by at least one nop from the ongoing write. rd or rd/a are not allowed before t wtr or t wtr_rr is met. write/a 5) 5) action write/a starts with issuing the command and ends twr afte r the first positive edge of clk following the last falling w dqs edge. act, pre, write, write/a, read 6) 6) during action write/a an act or a pre command on another bank is allowed any time. a new wr or wr/a command on another bank has to be separated by at least one nop from t he ongoing command. rd is not allowed before or t wtr or t wtr_rr is met. rd/a is not allowed during an ongoing write/a action. read 7) 7) action read starts with issuing the command and ends with t he first positive edge of clk following the last falling edge of r dqs. act, pre, write, write/a, read, read/a 8) 8) during action read and read/a an act or a pre command on anot her bank is allowed any time. a new rd or rd/a command on another bank has to be separated by at least one nop from the ongoing command. a wr or wr/a command on another bank has to meet t rtw . read/a 9) 9) action read/a starts with issuing the command and ends with the first positive edge of clk following the last falling edge of rdqs. act, pre, write, write/a, read, read/a 8) precharge 10) act, pre, write, write/a, read, read/a 11) precharge all 10) - power down entry 12) - idle activate 1) act power down entry 12) - auto refresh 13) - self refresh entry 12) - mode register set (mrs) 14) - extended mrs 14) - extended mrs 2 14) - power down power down exit 15) - self refresh self refresh exit 16) - hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 16 10102008-h7r1-i6ah 2.5 function truth table for cke table 7 function truth table ii (cke table) notes 1. cken is the logic step at clock edge n; cken-1 was the state of cke at the previous clock edge. 2. current state is the state of the gddr3 graphics ram immediately prior to clock edge n. 3. command is the command registered at clock edge n, and action is a result of command. 4. all states and sequences not shown are illegal or reserved. 5. desel or nop commands should be iss ued on any clock edges occurring during the t xsr period. a minimum of 1000 clock cycles is required before apply ing any other valid command. 10) action precharge and precharge all start with issuing the command and ends after t rp . 11) during action active an act command on another banks is allowed considering t rrd or t rrd_rr . a pre command on another bank is allowed any time. wr, wr/a, rd and rd/a are always allowed. 12) during power down and self refresh only the exit commands are allowed. 13) auto refresh starts with issuing the command and ends after t rfc . 14) actions mode register set, extended mo de register set and extended mode re gister 2 set start with issuing the command and ends after t mrd . 15) action power down exit starts with issuing the command and ends after t xpn . 16) action self refresh exit starts with issuing the command and ends after t xsc . cke n-1 cke n current state command action l l power down x stay in power down self refresh x stay in self refresh l h power down desel or nop exit power down self refresh desel or nop exit self refresh 5 h l all banks idle desel or nop entry precharge power down bank(s) active desel or nop entry active power down all banks idle auto refresh entry self refresh hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 17 10102008-h7r1-i6ah 3 boundary scan 3.1 general description the 1-gbit gddr3 incorporates a modified boundary scan test mode. this mode doesn?t operate in accordance with ieee standard 1149.1-1990. to save the current gddr3 ball-out, this mode will scan the par allel data input and output the scanned data through the wdqs0 pin controlled by sen. note: both pads bcs1 and a12 will be activated and could be accessed during boundary scan. 3.2 disabling the scan feature it is possible to operate the gddr3 without using the boundar y scan feature. sen (at u-4 of 136- ball package) should be tied low(vss) to prevent the device from entering the boundary scan mode. the other pins which are used for scan mode, res, mf, wdqs0 and cs will be operating at normal gddr3 f unctionalities when sen is deasserted. table 8 boundary scan exit order notes 1. when the device is in scan mode, the mirror function will be disabled and none of the pins are remapped. 2. since the other input of the mux for dm0 tied to gnd, the device will output the c ontinuous zeros after scanning a bit #67, if the chip stays in scan shift mode. 3. an unconnected cs1 and a12 on the board will be read as undefined. bit# ball bit# ball bit# ball bit# ball bit# ball bit# ball 1 d-3 13 e-10 25 k-11 37 r-10 49 l-3 61 g-4 2 c-2 14 f-10 26 k-10 38 t-11 50 m-2 62 f-4 3 c-3 15 e-11 27 k-9 39 t-10 51 m-4 63 f-2 4 b-2 16 g-10 28 m-9 40 t-3 52 k-4 64 g-3 5 b-3 17 f-11 29 m-11 41 t-2 53 k-3 65 e-2 6 a-4 18 g-9 30 l-10 42 r-3 54 k-2 66 f-3 7 b-10 19 h-9 31 n-11 43 r-2 55 l-4 67 e-3 8 b-11 20 h-10 32 m-10 44 p-3 56 j-3 9 c-10 21 h-11 33 n-10 45 p-2 57 j-2 10 c-11 22 j-11 34 p-11 46 n-3 58 h-2 11 d-10 23 j-10 35 p-10 47 m-3 59 h-3 12 d-11 24 l-9 36 r-11 48 n-2 60 h-4 hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 18 10102008-h7r1-i6ah table 9 scan pin description notes 1. when sen is asserted, no commands are to be executed by the gddr3. this applies both to user commands and manufacturing commands which may exist while res is deasserted. 2. the scan function can be used right after bringing up v dd / v ddq of the device. no initializat ion sequence of the device is required. after leaving the scan function it is requir ed to run through the complete initialization sequence. 3. in scan mode all terminations for cmd/add and dq, dm, rdqs and wdqs are switched off. 4. in a double-load clam-shell configuration, sen will be asserted to both devices. separate two soe ?s should be provided to top and bottom devices to access the scanned output. when either of the devices is in scan mode, soe for the other device which is not in a scan will be disabled. package ball symbol normal function type description v-9 ssh res input scan shift: capture the data input from the pad at logic low and shift the data on the chain at logic high. f-9 sck cs input scan clock: not a true clock, could be a single pulse or series of pulses. all scan inputs will be referenced to rising edge of the scan clock d-2 sout wdqs0 output scan output v-4 sen sen input scan enable: logic high enables the device into scan mode and will be disabled at logic low. must be tied to gnd when not in use. a-9 soe mf input scan output enable: enables (registered low) and disables (registered high) sout data. this pin will be tied to v dd or gnd through a resistor (typically 1 k for normal operation). tester needs to overdrive this pin to guarantee the required input logic level in scan mode. hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 19 10102008-h7r1-i6ah 4 functional description 4.1 mode register set command (mrs) the mode register stores the data for controlling the operation modes of the memory. it programs cas latency, test mode, dll reset , the value of the write latency and the burst length. the mode register must be written after power up to operate the sgram. during a moderegister set command the address inputs are sampled and stored in the mode register. the mode register content can only be set or changed when the chip is in idle state. for non-read commands following a mode register set a delay of t mrd must be met. to apply an mrs command, cs0 has to be used. the mode register bitmap is supported in two configurations. the first configuration is intended to support the mid-range- speed application. the second configuration supports higher clock cycles for cas latency and is therefore prepared to support high-speed application. the selected configuration is defined by bit0 of emrs2. figure 4 mode register set command 0 3 7 * & / . & / . 5 $ 6 & . ( & $ 6 : ( $ $ % $ ' r q w & d u h & 2 ' & r g h w r e h o r d g h g l q w r w k h u h j l v w h u & 6 & 2 ' % $ % $ hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 20 10102008-h7r1-i6ah figure 5 mode register bitmap for mid-range-speed application figure 6 mode register bitmap for high-speed application 0 3 % * 1 r w h 7 k h ' / / 5 h v h w f r p p d q g l v v h o i f o h d u l q j % / % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ ' / / & $ 6 / d w h q f \ % / $ $ % 7 $ ' / / 5 h v h w 1 r < h v $ 7 0 % $ : / ' h i d x o w 6 h w w l q j v : / $ $ $ 1 r u p d o 7 h v w p r g h $ p r g h / d w h q f \ $ $ $ 5 ) 8 $ o o r w k h u v 6 h t x h q w l d o 5 ) 8 % 7 $ % x u v w 7 \ s h % x u v w / h q j w k 7 h v w p r g h ' / / 5 h v h w : u l w h / d w h q f \ & $ 6 / d w h q f \ 0 3 % * 1 r w h 7 k h ' / / 5 h v h w f r p p d q g l v v h o i f o h d u l q j % / % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ ' / / & $ 6 / d w h q f \ % / $ $ % 7 $ ' / / 5 h v h w 1 r < h v $ 7 0 % $ : / ' h i d x o w 6 h w w l q j v : / $ $ $ 1 r u p d o 7 h v w p r g h $ p r g h / d w h q f \ $ $ $ 5 ) 8 $ o o r w k h u v 6 h t x h q w l d o 5 ) 8 % 7 $ % x u v w 7 \ s h % x u v w / h q j w k 7 h v w p r g h ' / / 5 h v h w : u l w h / d w h q f \ & $ 6 / d w h q f \ hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 21 10102008-h7r1-i6ah figure 7 mode register set timing 4.1.1 burst length read and write accesses to the gddr3 graphics ram are burst oriented with burst length of 4 and 8. this value must be programmed using the mode register set comm and (a0 .. a2). the burst length dete rmines the number of column locations that can be accessed for a given read or write command. when a read or write command is issued, a block of columns e qual to the burst length is effectively selected. all accesses for that burst take place within this block if a boundary is reached. the starting locati on within this block is determined by the two least significant bits a0 and a1 which are set internally to the fixed value of ze ro each.reserved states should not be use d, as unknown operation or incompatibility with future versions may result. 4.1.2 burst type accesses within a given bank must be programmed to be seq uential. this is done using the mode register set command (a3). this device does not support the burst interleave mode. table 10 burst definition the value applied at the balls a0 and a1 for the column address is ?don?t care?. burst length starting column address order of accesses within a burst (type = sequential) a2 a1 a0 4 ? x x 0-1-2-3 8 0 x x 0-1-2-3-4-5-6-7 1 x x 4-5-6-7-0-1-2-3 0 3 7 * & / . & / . 3 $ 0 5 6 1 2 3 $ & 1 2 3 w 5 3 w 0 5 ' & r p p d q g 1 2 3 5 ' 1 2 3 ' r q w & d u h 0 5 6 0 5 6 f r p p d q g 3 $ 3 5 ( $ / / f r p p d q g $ & $ q \ r w k h u f r p p d q g d v 5 ( $ ' w 0 5 ' 5 5 ' 5 ( $ ' f r p p d q g hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 22 10102008-h7r1-i6ah 4.1.3 cas latency the cas latency (cl) is the delay, in clock cycles, between the r egistration of a read command and the availability of the firs t bit of output data. if a read command is registered at clock edge n, and the latency is m clocks, the data will be av ailable nominally coincident with clock edge n+m. reserved states should not be used as unknown operation or incompatibility with futu re versions may result. 4.1.4 write latency the write latency, wl, is the delay, in clock cycles, between the registration of a wr ite command and the av ailability of the first bit of input data. 4.1.5 test mode the normal operating mode is selected by issuing a mode regi ster set command with bit a7 set to zero and bits a0-a6 and a8-a11 set to the desired value. 4.1.6 dll reset the normal operating mode is selected by issuing a mode regi ster set command with bit a8 set to zero and bits a0-a7 and a9-a11 set to the desired values. a dll reset is initiated by i ssuing a mode register set command with bit a8 set to one and bits a0-a7 and a9-a11 set to the desired values. the gddr3 graphics ram returns automatically in the normal mode of operations once the dll reset is completed. hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 23 10102008-h7r1-i6ah 4.2 extended mode register set command (emrs1) the extended mode register is used to control multiple operation modes of the device. th e most important one is the organization as a 1-cs or a 2- cs device. furthermore, it is used to set the output driver impedance value, the termination impedance value, the write recovery time value for write with autoprecharge. it is used as well to enable/disable the dll, to issue the vendor id. there is no default value for the extended mode register. theref ore it must be written after power up to operate the gddr3 graphics ram. the extended mode register can be programmed by performing a normal mode register set operation and setting the ba0 bit to high. all other bits of the emr register are reserved and should be set to low. the extended mode register must be loaded when all banks are idle and no burst are in progr ess. the controller must wait the specified time t mrd before initiating any subsequent operation ( figure 10 ). the timing of the emrs command operation is equivalent to the timing of the mrs command operation. to apply an emrs command, cs0 has to be used. figure 8 extended mode register set command 0 3 7 * & / . & / . 5 $ 6 & . ( & $ 6 : ( $ $ % $ ' r q w & d u h & 2 ' & r g h w r e h o r d g h g l q w r w k h u h j l v w h u & 6 & 2 ' % $ 0 r g h % $ hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 24 10102008-h7r1-i6ah figure 9 extended mode register bitmap for mid-range-speed application notes 1. this device supports two operation modes: 1-cs mode or 2- cs mode. for detail configurat ions and mode selection in relation to signals and ballouts. please refer to section 4.2.7 for further details. there are two bitmaps for the extended mode register. one bitmap shown in figure 9 is supposed to support mid-range- speed applications. the ot her bitmap shown in figure 10 is more focused on the high-speed application. both bitmaps distinguish different numbers in supported write recovery cl ock cycles. the mid-range bit map provides wr cycles from 4 to 11.the high-speed bitmap supports wr from 7 to 13. 0 3 % * ' d w d = % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ ' / / 9 : 5 5 w w 0 r g h $ $ 2 ' 7 g l v d e o h g 5 ) 8 7 h u p l q d w l r q = 4 = 4 2 x w s x w ' u l y h u , p s h g d q f h $ x w r f d o r k p v r k p v r k p v $ $ : 5 $ $ 5 ) 8 $ 9 h q g r u , ' 2 q 2 i i $ ' / / ( q d e o h ( q d e o h ' l v d e o h $ : 5 % $ % $ 6 h h 1 r w h e h o r z & $ = & k l s 6 h o h f w 0 r g h $ $ = 4 = 4 $ ' ' & 0 ' 7 h u p l q d w l r q = 4 = 4 ' h i d x o w 6 h w w l q j v hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 25 10102008-h7r1-i6ah figure 10 extended mode register bitmap for high-speed application notes 1. this device supports two operation modes: 1-cs mode or 2-cs mode. for detail configurations and mode selection in relation to signals and ballouts. please refer to section 4.2.7 for further details. 2. default termination values at power up. 3. the odt disable function disables all terminators on the device. 4. if the user activates bits in the extended mode register in an optional field, either the opt ional field is activated (if option implemented in the device) or no action is taken by the device (if option not implemented). 5. wr (write recovery time for auto precharge) in clock cycles is calculated by dividing t wr (in ns) and rounding up to the next integer (wr[cycles] = t wr [ns] / t ck [ns]). the mode register must be programmed to this value. 0 3 % * ' d w d = % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ ' / / 9 : 5 5 w w 0 r g h $ $ 2 ' 7 g l v d e o h g 5 ) 8 7 h u p l q d w l r q = 4 = 4 2 x w s x w ' u l y h u , p s h g d q f h $ x w r f d o r k p v r k p v r k p v $ $ : 5 $ $ 5 ) 8 $ 9 h q g r u , ' 2 q 2 i i $ ' / / ( q d e o h ( q d e o h ' l v d e o h $ : 5 % $ & $ = $ $ = 4 = 4 $ ' ' & 0 ' 7 h u p l q d w l r q = 4 = 4 % $ 3 o h d v h f k h f n w k h 1 r w h e h o r z & k l s 6 h o h f w 0 r g h hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 26 10102008-h7r1-i6ah figure 11 extended mode register set timing 4.2.1 dll enable the dll must be enabled for normal operation. dll enable is r equired during power-up initialization and upon returning to normal operation after having disabled the dll. (when the device exits self-refresh mode, the dll is enabled automatically). anytime the dll is enabled, 1000 cycles must occur before a read command can be issued. 4.2.2 wr the wr parameter is programmed using the register bits a4, a5 and a7. this integer parameter defines as a number of clock cycles the write recovery time in a write with autoprecharge operation. the following inequality has to be complied with: wr t wr , where t wr is defined as number of clock cycles. the high-speed bitmap supports wr from 7 to 13. the mid-range bitmap provides wr cycles from 4 to 11. 4.2.3 termination rtt the data termination, rtt, is used to set the value of the internal termination resi stors. the gddr3 dram supports zq / 4 and zq / 2 termination values. the termination may also be disabled for testing and other purposes. data -, address - and command - termination are disabled in parallel. the terminat ion rtt are controlled independently from the output driver impedance values. 4.2.4 output driver impedance the output driver impedance extended mode register is used to set the value of th e data output driver impedance. when the auto calibration is used, th e output driver impedance is set nominally to zq / 6. if the output driver impedance is changed to 35, 40 or 45 ohms the user needs to issue 16 aref commands separated by t rfc consecutively to make the change effective. the user must be aware that the command bus needs to be stable for a time of t ko after each aref. 4.2.5 vendor code and revision identification the manufacturer vendor code is selected by issuing an ex tended mode register set command with bit a10 set to 1 and bits a0-a9 and a11 set to the desired value. when the vendor code function is enabled the gddr3 dram will provide the 0 3 7 * & / . & / . ' r q w & d u h 3 $ ( 0 5 6 1 2 3 $ & 1 2 3 w 5 3 w 0 5 ' & r p p d q g ( 0 5 6 ( [ w h q g h g 0 5 6 f r p p d q g 3 $ 3 5 ( $ / / f r p p d q g $ & $ q \ f r p p d q g 1 2 3 hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 27 10102008-h7r1-i6ah qimonda vendor code on dq[3:0] and the revision identification on dq[7:4]. the code will be driven onto the dq bus after t ridon following the emrs command that sets a10 to 1. the vendor code and revision id will be driven on dq[7:0] until a new emrs command is issued with a10 set back to 0. after t ridoff following the second emrs command, the data bus is driven back to high. this second emrs command must be issued before init iating any subsequent operation. violating this requirement will result in unspecified operation. table 11 revision id and vendor code figure 12 timing of vendor code and revision id generation on dq[7:0] 4.2.6 address command termination the address and command termination is used to set the value of the internal termination resistors. the gddr3 dram supports zq / 4, zq / 2 and zq termination values. the mode register programming overwrites the programming during the chip initialization. revision identification qimonda vendor code dq[7:4] dq[3:0] 0101 0010 0 3 7 * & / . & / . 1 ' 1 ' & r p 1 ' 1 ' 1 ' 1 ' $ g g $ > @ $ 1 ' 1 ' 5 ' 4 6 ' 4 > @ $ 1 ' $ g g ( 0 5 6 ( 0 5 6 w 5 , ' r q 9 h q g r u & r g h d q g 5 h y l v l r q , ' w 5 , ' r i i ( 0 5 6 ( [ w h q g h g 0 r g h 5 h j l v w h u 6 h w & r p p d q g $ g g $ g g u h v v ' r q w & d u h 1 ' 1 2 3 r u ' h v h o h f w hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 28 10102008-h7r1-i6ah 4.2.7 chip select mode the gddr3 dram can be internally configured as two 512mbi t (2-cs mode) or one 1gbit device (1-cs mode). the pins cs1 and a12 are only active in two, resp. 1-cs mode and act either as the chip select for the second rank, or the row-address for the upper 4k-row-address range. if bit a5 from emrs2 (?merged mode ?) is set to 1 then the 2 operat ions mode will be inverted. table 12 chip select mode based on merged mode settings 1) 1-cs mode and no ball merged 2) 2-cs mode 3) 1-cs mode and ball merged configuration emrs1 emrs2 result note ba2 a5 cs mode merge mode signal ball config 1 0 0 a12 j2 1) config 2 1 0 cs1 j3 2) 01cs1 j3 config 3 1 1 a12 j3 3) hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 29 10102008-h7r1-i6ah 4.3 extended mode register 2 set command (emrs2) the extended mode register 2 is used to define the active bitmap of the mode register (mrs) and the extended mode register (emrs1). it is used to control ocd/odt impedance offsets, ballout merged mode, se lf refresh, and application modes. it can be programmed by performing a normal mode register set operation and setting the ba1 bit to high and ba0, ba2 bits to low. all bits defined as rfu in the bitmap are reserved and must be set to low. the extended mode register 2 must be loaded when all banks are idle and no burst are in progress. the controller must wait the specified time t mrd before initiating any subsequent operation. the ti ming of the emrs2 command operation is equivalent to the timing of the mrs command operation. figure 13 extended mode register 2 set command 0 3 7 * & / . & / . 5 $ 6 & . ( & $ 6 : ( $ $ % $ ' r q w & d u h & 2 ' & r g h w r e h o r d g h g l q w r w k h u h j l v w h u & 6 & 2 ' % $ hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 30 10102008-h7r1-i6ah figure 14 extended mode register 2 bitmap 4.3.1 app mode the gddr3 graphics ram provides two bitmaps for the mode r egister and the extended mode register respectively. the bitmaps are shown in the mrs and emrs chapters. the bit0 of the extended mode regsiter 2 de fines which one of the two bitmaps is active. there bit0 set to low enables the mid-range bitmap and bit0 set to high enables the high-speed bitmap. 4.3.2 ocd pull down offset the 1g gddr3 add the ability to add an offs et to the output impedance driver set using the bit a[1:0] of the emrs. a range from -3 to +3 can be chosen using a[11:9]. each steps corre spond to an approximate change of 1 ohms. the offset will be applied also on autocal value if selected. the offset will be applied also on autocal value if selected. with negative offset s teps the driver strength will be decreased and th e ron will be increased. with positive offset steps the driver strength will be increased and ron will be decreased. 0 3 % * 2 ' 7 3 x o o 8 s 2 i i v h w 6 ) 5 $ s s 0 r g h % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ % $ 6 h o i 5 h i u h v k $ 7 k h u p d o 6 h q v r u p v 2 & ' 3 x o o ' r z q 2 i i v h w $ > @ ' h i d x o w v 5 ) 8 5 ) 8 2 & ' 3 x o o ' r z q 2 i i v h w 2 ' 7 3 x o o 8 s 2 i i v h w $ > @ ' h i d x o w v 5 ) 8 ' h i d x o w v 6 h w w l q j v $ s s 0 r g h $ 1 r w h e r r n ' h v n w r s 0 h u j h g 0 r g h $ 1 r q 0 h u j h g 0 h u j h g 0 h u j h g 0 r g h hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 31 10102008-h7r1-i6ah 4.3.3 odt pull up offset the 1g gddr3 add the ability to add an offs et to the odt set using the bit a[3:2] of the emrs. a r ange from -3 to +3 can be chosen using a[8:6]. each steps correspond to an approximate change of 1.5 ohms. with negative offset steps the termination value will be increased. with positive offset steps the termination value will be decreased. 4.3.4 merged mode "merged mode" as been added to the emrs2 in order to merge the node a12/cs1 to a single ball (j-3) of the chip. default setting has both pins are using two differ ent balls (j-2 and j-3). please refer to section 4.2.7 for further details. 4.3.5 self refresh self refresh is used to control the timing of the refresh operation when the memory is in self refr esh. when bit a1 is set to 0 then the refresh timing is controlled by the embedded temperature sensor. in this mode of operation if the temperature is higher than 100c then the refresh will happen every 8ms. if t he temperature is below 100c t hen the refresh will happen every 32 ms. if the a1 is set to 1 then the refresh timing wi ll be independent from the tem perature and fixed to 8 ms. hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 32 10102008-h7r1-i6ah 4.4 extended mode register 3 set command (emrs3) the extended mode register 3 is used for setting the auto- calibration bit. the auto-calibration bit allows for either referencing to the external precis ion resistor or to fixed set of impedance for drivers and terminations. the mode register can be programmed by performing a normal mode register set operation and setting the ba0, ba1 bits to high and ba2 bit to low. all bits defined as rfu in the bitmap are reserved and must be set to low. the extended mode register 3 must be loaded when all banks are idle and no burst are in progress. the controller must wait the specified time t mrd before initiating any subsequent operat ion. the timing of the emrs3 command operation is equivalent to the timing of the mrs command operation. figure 15 extended mode register 3 set command figure 16 extended mode register 3 bitmap 0 3 7 * & / . & / . 5 $ 6 & . ( & $ 6 : ( $ $ % $ ' r q w & d u h & 2 ' & r g h w r e h o r d g h g l q w r w k h u h j l v w h u & 6 & 2 ' % $ 0 3 % * % $ $ $ $ $ $ $ $ $ $ $ $ $ % $ % $ ' l v d e o h ( q d e o h $ $ x w r f d o l e u d w l r q $ x w r f d o ' h i d x o w v h w w l q j v hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 33 10102008-h7r1-i6ah 4.4.1 autocalibration using this setting the odt and ocd can be disconnected from the autocalibration and become only dependant on the values defined by fuses. the detail operations are described as follows. (1) setting emrs3[11]=1 disables autocalibration for both ocd and odt. this option will force the behavior of the ocd and odt to mimic the operation when no zq resistor is present. (2 ) nmos pulldown offset emrs2[11:9] and pmos termination pullup offset emrs[8:6] will be applied to the results of emrs3[11 ], whether autocal results or fused results. (3) the fused results for ocd in (1) will be 40 ohms if "autocal" mode is selected in emrs1[1:0]. other wise the settings for 35,40,45 ohms will be used if selected. (4) the fused results for ca, dq odt in (1 ) will be 60 ohms if zq/4 is selected, 120 ohms if zq/2 is selected, and will be 240 ohms if zq is selected in the field emrs1[9:8] (ca) and emrs1[3:2]. the driver and termination impedance settings remain in normal operation when emrs3[11]=0 (as default). 4.5 voltage change sequence 4.5.1 change from 1.8 v to 1.5 v 1. start normal operation at 1.8 v 2. close all banks 3. issue srefen 4. set target frequency 5. set v dd to 1.5 v 6. wait until clock and v dd are stable 7. issue srefex and wait t rfc 8. wait t xsrd dll locking time before aref is issued 9. adjust ac timings to the target frequency 10. start normal operations 4.5.2 change from 1.5 v to 1.8 v 1. start normal operation at 1.5 v 2. close all banks 3. adjust ac timings to the target frequency 4. issue srefen 5. set v dd to 1.8 v 6. set target frequency 7. wait until clock and v dd are stable 8. issue srefex and wait t rfc 9. wait t xsrd dll locking time before aref is issued 10. start normal operations hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 34 10102008-h7r1-i6ah 5 electrical characteristics 5.1 absolute maximum ratings and operation conditions table 13 absolute maximum ratings attention: stresses above the max. value s listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 5.2 dc operation conditions 5.2.1 recommended power & dc operation conditions table 14 power & dc operation conditions (0 c t c 95 c) parameter symbol rating unit min. max. power supply voltage v dd -0.5 2.5 v power supply voltage for output buffer v ddq -0.5 2.5 v input voltage v in -0.5 2.5 v output voltage v out -0.5 2.5 v storage temperature t stg -55 +150 c junction temperature t j ?+125 c short circuit output current i out ?50ma parameter symbol limit values unit note min. typ. max. power supply voltage v dd / v ddq 1.7 1.8 1.9 v 1)2)3) v dd / v ddq 1.455 1.5 1.545 v 1)2)4) hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 35 10102008-h7r1-i6ah 1) under all conditions v ddq must be less than or equal to v dd 2) v ddq tracks with v dd . ac parameters are measured with v dd and v ddq tied together 3) for 1.8 v v dd / v ddq power supply 4) for 1.5 v v dd / v ddq power supply 5) v ref is expected to equal 70% of v ddq for the transmitting device and to track variations in the dc level of the same. peak-to-peak noise on v ref may not exceed 2% v ref (dc). thus, from 70% of v ddq , v ref is allowed 19mv for dc error and an additional 27mv for ac noise 6) i il and i ol are measured with odt disabled 5.3 dc & ac logic input levels table 15 dc & ac logic input levels (0 c t c 95 c) 1) for 1.8 v v dd / v ddq power supply 2) for 1.5 v v dd / v ddq power supply 3) the dc values define where the input slew rate requirements ar e imposed, and the input signal mu st not violate these levels i n order to maintain a valid level. 4) input slew rate = 3 v/ns. if the input slew rate is less than 3 v/ns, input timing may be compro mised. all slew rates are measu red between v il (ac) and v ih (ac). reference voltage v ref 0.69* v ddq ?0.71* v ddq v 5) output low voltage v ol(dc) ??0.8v 3) ? ? 0.62 v 4) input leakage current i il ?5.0 ? +5.0 ? 6) clk input leakage current i ilc ?5.0 ? +5.0 ? output leakage current i ol ?5.0 ? +5.0 ? 6) parameter symbol limit values unit note min. max. input logic high voltage, dc v ih (dc) v ref + 0.15 ? v 1)3) v ref + 0.12 ? v 2)3) input logic low voltage, dc v il (dc) ? v ref -0.15 v 1)3) ? v ref - 0.12 v 2)3) input logic high voltage, ac v ih (ac) v ref + 0.25 ? v 1)4)5) v ref + 0.2 ? v 2)4)5) input logic low voltage, ac v il (ac) ? v ref - 0.25 v 1)4)5) ? v ref - 0.2 v 2)4)5) input logic high, dc, reset pin v ihr (dc) 0.65 v ddq v ddq + 0.3 v input logic low, dc, reset pin v ilr (dc) -0.3 0.35 v ddq v input logic high, dc, mf pin v ihmf (dc) v dd v dd + 0.3 v 6) input logic low,dc, mf pin v ilmf (dc) ?0.3 0 v parameter symbol limit values unit note min. typ. max. hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 36 10102008-h7r1-i6ah 5) v ih overshoot: v ih (max) = v ddq +0.5v for a pulse width 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. v il undershoot: v il (min) = 0 v for a pulse width 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. 6) the mf pin must be hard-wired on board to either v dd or v ss . 5.4 differential clock dc and ac levels table 16 differential clock dc and ac input conditions (0 c t c 95c) 5.5 output test conditions figure 17 output test circuit parameter symbol limit values unit note min. max. clock input mid-point voltage, clk and clk v mp (dc) 0.7 v ddq ? 0.10 0.7 v ddq + 0.10 v 1) 1) all voltages referenced to v ss. clock input voltage level, clk and clk v in (dc) 0.42 v ddq + 0.3 v 1)2) 2) for 1.8 v v dd / v ddq power supply 0.35 v ddq + 0.3 v 1)3) 3) for 1.5 v v dd / v ddq power supply clock dc input differential voltage, clk and clk v id (dc) 0.3 v ddq v 1) clock ac input differential voltage, clk and clk v id (ac) 0.5 v ddq + 0.5 v 1)2)4) 4) v id is the magnitude of the difference between the input level on clk and the input level on clk . 0.4 v ddq + 0.5 v 1)3)4) ac differential crossing point input voltage v ix (ac) 0.7 v ddq ? 0.15 0.7 v ddq + 0.15 v 1)2)5) 5) the value of v ix is expected to equal 0.7 v ddq of the transmitting device and must track variations in the dc level of the same. 0.7 v ddq ? 0.12 0.7 v ddq + 0.12 v 1)3)5) 0 3 % * ' 4 2 k p 7 h v w s r l q w ' 4 6 9 ' ' 4 hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 37 10102008-h7r1-i6ah 5.6 pin capacitances table 17 pin capacitances (vddq = 1.8 v, ta = 25c, f = 1 mhz) 5.7 driver current characteristics 5.7.1 driver iv characteristics at 40 ohms figure 18 represents the driver pull-down and pull-up iv charac teristics under process, volt age and temperature best and worst case conditions. the actual driver pull-down and pull-up current must lie between these two bounding curves. the value of the external zq resistor is 240 , setting the nominal driver output impedance to 40 . figure 18 40 ohm driver pull-down and pull-up characteristics table 18 lists the numerical values of the mi nimum and maximum allowed values of t he output driver pull-down and pull-up iv characteristics. parameter symbol min. max. unit note input capacitance: a0-a11,a12, , ba0-2, cke, cs , cas , ra s, we , cke, res,clk,clk ci,cck 1.0 2.5 pf input capacitance: dq0-dq31, rdqs0-rdqs3, wdqs0-wdqs3, dm0-dm3 cio 2.0 3.0 pf 0 3 ( * 3 x o o ' r z q & k d u d f w h u v w l f v 9 r x w 9 , r x w p $ 0 3 ( * 3 x o o 8 s & k d u d f w h u v w l f v 9 ' ' 4 9 r x w 9 , r x w p $ hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 38 10102008-h7r1-i6ah table 18 programmed driver iv characteristics at 40 ohm 5.7.2 termination iv characteristic at 60 ohms figure 19 represents the dq termination pull-up iv characteristic u nder process, voltage and temperature best and worst case conditions. the actual dq termination pull-up current must li e between these two bounding curves. the value of the external zq resistor is 240 , setting the nominal dq termination impedance to 60 . (extended mode register programmed to zq/4). voltage (v) pull-down curren t (ma) pull-up current (ma) minimum maximum minimum maximum 0.1 2.32 3.04 -2.44 -3.27 0.2 4.56 5.98 -4.79 -6.42 0.3 6.69 8.82 -7.03 -9.45 0.4 8.74 11.56 -9.18 -12.37 0.5 10.70 14.19 -11.23 -15.17 0.6 12.56 16.72 -13.17 -17.83 0.7 14.34 19.14 -15.01 -20.37 0.8 16.01 21.44 -16.74 -22.78 0.9 17.61 23.61 -18.37 -25.04 1.0 19.11 26.10 -19.90 -27.17 1.1 20.53 28.45 .21.34 -29.17 1.2 21.92 30.45 -22.72 -31.25 1.3 23.29 32.73 -24.07 -33.00 1.4 24.65 34.95 -25.40 -35.00 1.5 26.00 37.10 -26.73 -37.00 1.6 27.35 39.15 -28.06 -39.14 1.7 28.70 41.01 -29.37 -41.25 1.8 30.08 42.53 -30.66 -43.29 1.9 ? 43.71 ? -45.23 2.0 ? 44.89 ? -47.07 hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 39 10102008-h7r1-i6ah figure 19 60 ohm active termination characteristic table 19 lists the numerical values of the minimum and maximum allowed valu es of the output dr iver termination iv characteristic. table 19 programmed terminator char acteristics at 60 ohm voltage (v) terminator pull-up current (ma) voltage (v) terminator pull-up current (ma) minimum maximum minimum maximum 0.1 -1.63 -2.18 1.1 -14.23 -19.45 0.2 -3.19 -4.28 1.2 -15.14 -20.83 0.3 -4.69 -6.30 1.3 -16.04 -22.00 0.4 -6.12 -8.25 1.4 -16.94 -23.33 0.5 -7.49 -10.11 1.5 -17.82 -24.67 0.6 -8.78 -11.89 1.6 -18.70 -26.09 0.7 -10.01 -13.58 1.7 -19.58 -27.50 0.8 -11.16 -15.19 1.8 -20.44 -28.86 0.9 -12.25 -16.69 1.9 ? -30.15 1.0 -13.27 -18.11 2.0 ? -31.38 0 3 ( * 2 k p 7 h u p l q d w l r q & k d u d f w h u v w l f v 9 ' ' 4 9 r x w 9 , r x w p $ hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 40 10102008-h7r1-i6ah 5.8 termination iv characteristic at 120 ohms figure 20 represents the dq or add/cmd termination pull-up iv ch aracteristic under process, voltage and temperature best and worst case conditions. the actual termination pull-up curre nt must lie between these two bounding curves. the value of the external zq resistor is 240 , setting the nominal termination impedance to 120 . (extended mode register programmed to zq/2 for dq terminations or cke = 0 at the r es transition during power-up for add/cmd terminations). figure 20 120 ohm active termination characteristic table 20 lists the numerical values of the minimum and maximum allowed values of the termination iv characteristic. table 20 programmed terminator characteristics of 120 ohm voltage (v) terminator pull-up current (ma) voltage (v) terminator pull-up current (ma) minimum maximum minimum maximum 0.1 -0.81 -1.09 1.1 -7.11 -9.72 0.2 -1.60 -2.14 1.2 -7.57 -10.42 0.3 -2.34 -3.15 1.3 -8.02 -11.00 0.4 -3.06 -4.12 1.4 -8.47 -11.67 0.5 -3.74 -5.06 1.5 -8.91 -12.33 0.6 -4.39 -5.94 1.6 -9.35 -13.05 0.7 -5.00 -6.79 1.7 -9.79 -13.75 0.8 -5.58 -7.59 1.8 -10.22 -14.43 0.9 -6.12 -8.35 1.9 ? -15.08 1.0 -6.63 -9.06 2.0 ? -15.69 0 3 ( * 2 k p 7 h u p l q d w l r q & k d u d f w h u v w l f v 9 ' ' 4 9 r x w 9 , r x w p $ hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 41 10102008-h7r1-i6ah 5.9 termination iv characteristic at 240 ohms figure 21 represents the add/cmd termination pull-up iv characteri stic under process, voltage and temperature best and worst case conditions. the actual add/cmd termination pull- up current must lie between these two bounding curves. the value of the external zq resistor is 240 , setting the nominal termination impedance to 240 . (cke = 1at the res transition during power-up for add/cmd terminations). figure 21 240 ohm active termination characteristic table 21 lists the numerical values of the minimum and ma ximum allowed values of the add/cmd termination iv characteristic. table 21 programmed terminator characteristics at 240 ohm voltage (v) terminator pull-up current (ma) voltage (v) terminator pull-up current (ma) minimum maximum minimum maximum 0.1 -0.41 -0.55 1.1 -3.56 -4.86 0.2 -0.80 -1.07 1.2 -3.79 -5.21 0.3 -1.17 -1.58 1.3 -4.01 -5.50 0.4 -1.53 -2.06 1.4 -4.23 -5.83 0.5 -1.87 -2.53 1.5 -4.46 -6.17 0.6 -2.20 -2.97 1.6 -4.68 -6.52 0.7 -2.50 -3.40 1.7 -4.90 -6.88 0.8 -2.79 -3.80 1.8 -5.11 -7.21 0.9 -3.06 -4.17 1.9 ? -7.54 1.0 -3.32 -4.53 2.0 ? -7.85 0 3 ( * 2 k p 7 h u p l q d w l r q & k d u d f w h u v w l f v 9 ' ' 4 9 r x w 9 , r x w p $ hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 42 10102008-h7r1-i6ah 5.10 operating currents 5.10.1 operating current ratings for hyb18h1g321a2f table 22 operating current ratings ( 0 c t c 95 c) parameter symbol limit values unit note -8 ?10 ?14 typ. typ. typ. operating current i dd0 tbd tbd tbd ma 1)2)3) 1) idd specifications are tested afte r the device is properly initialized. 2) input slew rate = 3v/ns. 3) measured with output open and on die termination off. i dd1 tbd tbd tbd ma 1)2)3) precharge power-down standby current i dd2p tbd tbd tbd ma 1)2)3) active power-down standby current i dd3p tbd tbd tbd a 1)2)3) active standby current i dd3n tbd tbd tbd ma 1)2)3) operating current burst read i dd4r tbd tbd tbd ma 1)2)3) operating current burst write i dd4w tbd tbd tbd ma 1)2)3) auto-refresh current ( t rc =min( t rfc )) i dd5b tbd tbd tbd ma 1)2)3) self refresh current i dd6 tbd tbd tbd ma 1)2)3)4) 4) enables on-chip refresh and address counter. operating current 1-cs i dd7 tbd tbd tbd ma 1)2)3) 2-cs tbd tbd tbd ma 1)2)3) hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 43 10102008-h7r1-i6ah 5.11 operating current measurement conditions table 23 operating current measurement conditions notes 1. 0 c tc 95 c 2. data bus consists of dq, dm, wdqs. 3. definitions for idd: low is defined as vin = 0.4 vddq; high is defined as v in = v ddq ; stable is defined as inputs are stable at a high level. switching is defined as inpu ts are changing between high and low ever y clock cycle for address and control signals, and inputs changing 50% of each data transfer for dq signals. symbol parameter/condition i dd0 operating current - one bank, activate - precharge t ck =min( t ck ), t rc =min( t rc ) databus inputs are switchi ng; address and control inputs are switching, cs = high between valid commands. i dd1 operating current - one bank, activate - read - precharge one bank is accessed with t ck =min( t ck ), t rc =min( t rc ), cl = cl(min), address and control inputs are switching; cs = high between valid commands. i out =0 ma i dd2p precharge power-down standby current all banks idle, power-down mode, cke is low, t ck =min( t ck ), data bus inputs are stable (high). i dd3p active power-down standby current one bank active, cke is low, address and control inputs are stable (high); da ta bus inputs are stable (high); standard active power-down mode. i dd3n active standby current one bank active, cs is high, cke is high, t ras = t ras,max , t ck =min( t ck ); address and control inputs are switching; data bus inputs are switching. i dd4r operating current - burst read one bank active; continuous read bursts, cl = cl(min); t ck =min( t ck ); t ras = t ras,max ; address and control inputs are switching; iout = 0 ma. i dd4w operating current - burst write one bank active; continuous write bursts; t ck =min( t ck ); address and control inputs are switching; data bus inputs are switching. i dd5b burst auto refresh current refresh command at t rfc =min(t rfc ); t ck =min( t ck ); cke is high, cs is high between all valid commands; other command and address inputs are switchi ng; data bus inputs are switching. i dd6 self refresh current cke max( v il ), external clock off, ck and ck low; address and control input s are stable (high); data bus inputs are stable (high). i dd7 operating bank interleave read current 1. 1-cs mode: all banks interleaving with cl = cl(min); t rcd = t rcdrd (min); t rrd = t rrd (min); i out =0 ma; address and control inputs are stable (high) during d eselect; data bus inputs are switching. hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 44 10102008-h7r1-i6ah 5.12 ac timings for hyb18h1g321a2f table 24 timing parameters for hyb18h1g321a2f parameter symbol -8 -10 -14 unit note min. max. min. max. min. max. system frequency cl = 15 f ck15 250 1200 ? ? ? ? mhz 1) cl = 12 f ck12 250 1000 250 1000 ? ? mhz 1) cl = 11 f ck11 250 900 250 900 ? ? mhz 1) cl = 10 f ck10 250 850 250 850 250 700 mhz 1) cl = 9 f ck9 250 750 250 750 250 650 mhz 1) cl = 8 f ck8 250 650 250 650 250 550 mhz 1) cl = 7 f ck7 250 600 250 600 250 500 mhz 1) clock cycle to cycle period jitter t jit(cc) 0.06 0.06 0.06 t ck 2)3) clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck 2)3) clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck 2)3) minimum clock half period t hp 0.45 ? 0.45 ? 0.45 ? t ck 2) command and address setup and hold timing address/command input setup time t is 0.22 ? 0.24 ? 0.35 ? ns 4)5) address/command input hold time t ih 0.22 ? 0.24 ? 0.35 ? ns 4)5) address/command input pulse width t ipw 0.7 ? 0.7 ? 0.7 ? t ck mode register set timing mode register set cycle time t mrd 6?6?6? t ck 6)7) mode register set to read timing t mrdr 12 ? 12 ? 12 ? t ck 6)7) row timing row cycle time t rc 44 ? 39 ? 34 ? t ck row active time t ras 28 ? 25 ? 22 ? t ck 8) act(a) to act(b) command period t rrd 10 ? 9 ? 7 ? t ck act(a) to act(b) command period (different rank) t rrd_rr 1?1?1? t ck 9) row precharge time t rp 16 ? 14 ? 12 ? t ck row to column delay time for reads t rcdrd 15 ? 13 ? 11 ? t ck row to column delaytime for writes t rcdwr min: max[( t rcdrd (min) - (wl + 1)); 2] max: ? t ck four active windows t faw 42 ? 36 ? 35 ? t ck 10) column timing cas(a) to cas(b) command period t ccd 2?2?2? t ck 10) write to read command delay t wtr 8?7?6? t ck 11) write to read command delay (different rank) t wtr_rr bl/2 - 1 ? bl/2 - 1 ? bl/2 - 1 ? t ck 9)12) write to write command delay (different rank) t wtw_rr bl/2 ? bl/2 ? bl/2 ? t ck 9) hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 45 10102008-h7r1-i6ah read to write command delay t rtw min: (cl + bl/2 + 2 - wl) max: ? t ck 13) read to read command delay (different rank) t rtr_rr 2?2?2? t ck 9) write cycle timing parameters write command to first wdqs latching transition t dqss wl- 0,25 wl+ 0,25 wl- 0,25 wl+ 0,25 wl- 0,25 wl+ 0,25 t ck data-in and data mask to wdqs setup time t ds 0.12 ? 0.14 ? 0.18 ? ns 4)14) data-in and data mask to wdqs hold time t dh 0.12 ? 0.14 ? 0.18 ? ns 4)14) data-in and dm input pulse width (each input) t dipw 0.4 ? 0.4 ? 0.4 ? t ck 2) dqs input low pulse width t dqsl 0.4 ? 0.4 ? 0.4 ? t ck dqs input high pulse width t dqsh 0.4 ? 0.4 ? 0.4 ? t ck dqs write preamble time t wpre 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs write postamble time t wpst 0.75 1.25 0.75 1.25 0.75 1.25 t ck write recovery time t wr 15 ? 13 ? 10 ? t ck 11) read cycle timing parameters for data and data strobe data access time from clock t ac -0.2 0.2 -0.21 0.21 -0.25 0.25 ns read preamble t rpre 0.75 1.25 0.75 1.25 0.75 1.25 t ck 2) read postamble t rpst 0.75 1.25 0.75 1.25 0.75 1.25 t ck data-out high impedance time from clk t hz t acmin t acmax t acmin t acmax t acmin t acmax ns data-out low impedance time from clk t lz t acmin t acmax t acmin t acmax t acmin t acmax ns dqs edge to clock edge skew t dqsck -0.2 0.2 -0.21 0.21 -0.25 0.25 ns dqs edge to output data edge skew t dqsq ? 0.11 ? 0.12 ? 0.16 ns 4) data hold skew factor t qhs ? 0.11 ? 0.12 ? 0.16 ns data output hold time from dqs t qh t hp - t qhs ns refresh/power down timing for data and data strobe refresh period (8192 cycles) t ref ?32?32?32ms average periodic auto refresh interval t refi 3.9 3.9 3.9 s delay from aref to next act/ aref t rfc 52 ? 52 ? 59 ? ns self refresh exit time t xsrd 1000 ? 1000 ? 1000 ? t ck self refresh exit followed non read command t xsnr 100 ? 100 ? 100 ? t ck 15) power down exit time t xpn 9?7?6? t ck other timing parameters res to cke setup timing t ats 10 ? 10 ? 10 ? ns res to cke hold timing t ath 10 ? 10 ? 10 ? ns termination update keep out timing t ko 10 ? 10 ? 10 ? ns rev, id emrs to dq on timing t ridon ?20?20?20ns rev, id emrs to dq off timing t ridoff ?20?20?20ns 1) f ck (min), f ck (max) for dll on mode 2) t hp is the lesser of t cl minimum actually applied to the device clk, bclk inputs. 3) clk and bclk input slew rate must be greater than 3 v/ns 4) the input reference level for signals other than clk and bclk is v ref parameter symbol -8 -10 -14 unit note min. max. min. max. min. max. hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 46 10102008-h7r1-i6ah 5) command/address input slew rate = 3 v/ns. if the slew rate is less than 3 v/ns, timing is no longer referenced to the midpoin t but to the v il(ac) maximum and v ih(ac) minimum points 6) t mrd is defined from mrs to any other command then read. 7) this value of t mrd applies only to the case where the dll reset bit is not activated. 8) t ras,max is 8* t ref . 9) the parameter is defined for commands issued to rank m following rank n where m different than n. for all other type of acces s, standard timing parameters do apply. 10) wtr and t wr start at the first rising edge of clk after the last valid (failing) wdqs edge of the slowest wdqs edge. 11) please round up t rtw to the next integer of t ck 12) t wtr_rr parameter is operated under the conditions that cl >= wl + 3 (for bl=4) and cl >= wl+ 5 (for bl=8) 13) the parameter is defined per byte. 14) dq and dm input slew rate must not deviate from wdqs by more than 10 percent. if the dq/dm/wdqs slew rate is less than 3 v/n s, timing is no longer referenced to the midpoint but to the vil(ac) maximum and vih(ac) minimum points 15) autocalibration must be turned off to use fixed impedance values hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 47 10102008-h7r1-i6ah 6 package 6.1 package outline figure 22 package outline pg-tfbga-136-065 note: the package is conforming with jedec mo-207i, var dr-z. ) 3 2 b 3 * 7 ) % * $ b b hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 48 10102008-h7r1-i6ah 6.2 package thermal characteristics table 25 pg-tfbga-136 package thermal resistances notes 1. theta_ja: junction to ambient thermal resistance. the values have been obtained by simulation using the conditions stated in the jedec jesd-51 standard. 2. theta_jb: junction to board t hermal resistance. the value has been obtained by simulation. 3. theta_jc: junction to case thermal resistance. the value has been obtained by simulation. theta_ja theta_jb theta_jc jedec board 1s0p 2s2p air flow 0 m/s 1 m/s 3 m/s 0 m/s 1 m/s 3 m/s - - k/w 4032272219175 2 hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 49 10102008-h7r1-i6ah list of illustrations figure 1 ballout 1-gbit gddr3 graphics ram in 1-cs mode in non merged mode(top view; mf = low) . . . . . . . . . . 6 figure 2 ballout 1-gbit gddr3 graphics ram in 2-cs mode in non merged mode(top view; mf = low) . . . . . . . . . . 7 figure 3 ballout 1gbit gddr3 graphics ram in merged mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4 mode register set command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 5 mode register bitmap for mid-range-speed application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 6 mode register bitmap for high-speed application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7 mode register set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8 extended mode register set command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9 extended mode register bitmap for mid-range-speed application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 10 extended mode register bitmap for high-speed application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 11 extended mode register set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 12 timing of vendor code and revision id generation on dq[7 :0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 13 extended mode register 2 set command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 14 extended mode register 2 bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 15 extended mode register 3 set command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 16 extended mode register 3 bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 17 output test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 18 40 ohm driver pull-down and pull-up characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 19 60 ohm active termination characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 20 120 ohm active termination characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 21 240 ohm active termination characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 22 package outline pg-tfbga-136-065 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 50 10102008-h7r1-i6ah list of tables table 1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2 ball description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3 ball assignment with mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4 command overview for 1-cs mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5 command overview for 2-cs mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6 function truth table i. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 7 function truth table ii (cke table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 8 boundary scan exit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9 scan pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 10 burst definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 11 revision id and vendor code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 12 chip select mode based on merged mode settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 14 power & dc operation conditions (0 c t c 95 c). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 15 dc & ac logic input levels (0 c t c 95 c). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 16 differential clock dc and ac input conditions (0 c t c 95c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 17 pin capacitances (vddq = 1.8 v, ta = 25c, f = 1 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 18 programmed driver iv characteristics at 40 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 19 programmed terminator characteristics at 60 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 20 programmed terminator characteristics of 120 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 21 programmed terminator characteristics at 240 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 22 operating current ratings ( 0 c t c 95 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 23 operating current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 24 timing parameters for hyb18h1g321a2f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 25 pg-tfbga-136 package thermal resistances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 51 10102008-h7r1-i6ah contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 ball definition and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 mirror function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.1 command table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4.1 function truth table for more than one activated bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5 function truth table for cke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 disabling the scan feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 mode register set command (mrs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1.1 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1.2 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1.3 cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1.4 write latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1.5 test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1.6 dll reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2 extended mode register set command (emrs1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.1 dll enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2.2 wr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2.3 termination rtt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2.4 output driver impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2.5 vendor code and revision identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2.6 address command termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2.7 chip select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3 extended mode register 2 set command (emrs2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3.1 app mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3.2 ocd pull down offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3.3 odt pull up offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3.4 merged mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3.5 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.4 extended mode register 3 set command (emrs3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.4.1 autocalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.5 voltage change sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.5.1 change from 1.8 v to 1.5 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.5.2 change from 1.5 v to 1.8 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1 absolute maximum ratings and operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2 dc operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2.1 recommended power & dc operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3 dc & ac logic input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.4 differential clock dc and ac levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.5 output test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 52 10102008-h7r1-i6ah 5.6 pin capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.7 driver current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.7.1 driver iv characteristics at 40 ohms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.7.2 termination iv characteristic at 60 ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.8 termination iv characteristic at 120 ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.9 termination iv characteristic at 240 ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.10 operating currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.10.1 operating current ratings for hyb18h1g321a2f. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.11 operating current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.12 ac timings for hyb18h1g321a2f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.2 package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 edition 2008-10 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2008. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein an d/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any ki nd, including without limitation warranties of non-infringement of in tellectual property righ ts of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. under no circumstances may the qimonda product as referred to in this internet data sheet be used in 1. any applications that are intended for military usage (including but not limited to weaponry), or 2. any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining or protecting human life (such applications, devices an d systems collectively referred to as "critical systems"), if a) a failure of the qimonda product can reasonable be expected to - directly or indirectly - (i) have a detrimental effect on such critical systems in terms of reliability, effectiveness or safety; or (ii) cause the failure of such critical systems; or b) a failure or malfunction of such critical systems ca n reasonably be expected to - directly or indirectly - (i) endanger the health or the life of the user of such critical systems or any other person; or (ii) otherwise cause material damages (including but not lim ited to death, bodily injury or significant damages to property, whether tangible or intangible). www.qimonda.com advance internet data sheet |
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